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ISBN-10: 0738118192

ISBN-13: 9780738118192

A regular syntax and semantics for VHDL sign up move point (RTL) synthesis is outlined. The subset of IEEE 1076 (VHDL) that's compatible for RTL synthesis is outlined, in addition to the semantics of that subset for the synthesis area.

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Extra info for 1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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All rights reserved. 6-1999 IEEE STANDARD FOR VHDL unconstrained_array_definition ::= array ( index_subtype_definition { , index_subtype_definition } ) of element_subtype_indication constrained_array_definition ::= array index_constraint of element_subtype_indication index_subtype_definition ::= type_mark range <> index_constraint ::= ( discrete_range { , discrete_range } ) discrete_range ::= discrete_subtype_indication | range range ::= range_attribute_name | simple_expression direction simple_expression Supported: — Array_type_definition — Unconstrained_array_definition — Constrained_array_definition — Index_subtype_definition — Index_constraint — Discrete_range The index constraint shall contain exactly one discrete range.

3-1997). 9 Loop statement loop_statement ::= [ loop_label: ] [ iteration_scheme ] loop sequence_of_statements end loop [ loop_label ] ; iteration_scheme ::= while condition | for loop_parameter_specification parameter_specification ::= identifier in discrete_range discrete_range ::= discrete_subtype_indication | range Copyright © 2000 IEEE. All rights reserved. 6-1999 IEEE STANDARD FOR VHDL Supported: — Loop_statement — Iteration_scheme — Parameter_specification — Discrete_range Not supported: — While The iteration scheme shall not be omitted.

6-1999 IEEE STANDARD FOR VHDL Not supported: — — — Interface_file_declaration Mode linkage Reserved word bus Generic interface constant declarations shall have a subtype indication of an integer type or of a subtype thereof. The static expression shall be ignored in port interface lists and formal parameter lists, except for interface constant declarations that shall be supported. a) Interface lists interface_list ::= interface_element {; interface_element} interface_element ::= interface_declaration Supported: — — Interface_list Interface_element b) Association lists association_list ::= association_element {, association_element} association_element ::= [formal_part =>] actual_part formal_part ::= formal_designator | function_name( formal_designator ) | type_mark( formal_designator ) formal_designator ::= generic_name | port_name | parameter_name actual_part ::= actual_designator | function_name( actual_designator ) | type_mark( actual_designator ) actual_designator ::= expression | signal_name | variable_name | file_name | open 32 Copyright © 2000 IEEE.

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1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis


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