By Weixia Xu, Liquan Xiao, Jinwen Li, Chengyi Zhang, Zhenzhen Zhu
This ebook constitutes the refereed complaints of the 18th nationwide convention on desktop Engineering and expertise, NCCET 2014, held in Guiyang, China, in the course of July/August 2014. The 18 papers awarded have been conscientiously reviewed and chosen from eighty five submissions. they're equipped in topical sections on processor structure; machine program and software program optimization; expertise at the horizon.
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Extra resources for Computer Engineering and Technology: 18th CCF Conference, NCCET 2014, Guiyang, China, July 29 – August 1, 2014, Revised Selected Papers
7 Software platform This paper utilizes the languages Python and C to implement the performance analysis and design space exploration. The 12 main programs with 3100 code lines are shown in Table 4. Table 4. py simulated_annealing. 2 F. Qin et al. Experiment Parameters and Benchmark Programs Our design space consists of 729 design points. The design space is spanned by the independent design parameters enumerated in Table 5. Table 5. Microarchitectural design parameters Parameters fetchWidth decodeWidth renameWidth issueWidth commitWidth numROBEntries Value Range 3, 5, 7 2, 4, 6 2, 4, 6 4,6 , 8 4, 6, 8 8, 13, 18 Number 3 3 3 3 3 3 The test programs used in this study are Laplace transform and the three core code segments of the “8 Queen” problem.
Second collects multicast destination node IDs into an array dst_id_array (Step 8-14). Third sets the first element of dst_id_array as the best candidate node ID and calculates the manhattan distance between the current node and the best candidate node in layer 0 (Step15-17). Forth the best candidate node with the minimum manhattan distance to the current node is found (Step 18-25). Finally, the productive direction(s) can be acquired according to the position of the best candidate node to the current node in (Step 26).
Qin et al. Conclusion and Future Works The increasing complexity of superscalar microprocessor design leads to increasing difficulty and cost for performance analysis and design space exploration. This paper proposes a HMCPA method for the design space exploration of superscalar microprocessors. A dependence graph and critical path analysis can analyze processors in depth to identify the bottleneck in fine grain. HMCPA utilizes the bottleneck at the current design point to guide design improvement and can ensure that such improvement is forwarded to the optimum.
Computer Engineering and Technology: 18th CCF Conference, NCCET 2014, Guiyang, China, July 29 – August 1, 2014, Revised Selected Papers by Weixia Xu, Liquan Xiao, Jinwen Li, Chengyi Zhang, Zhenzhen Zhu