By Michael J. Flynn, Wayne Luk
The subsequent iteration of desktop process designers might be much less all for info of processors and stories, and extra focused on the weather of a method adapted to specific functions. those designers could have a basic wisdom of processors and different parts within the process, however the good fortune in their layout depends upon the talents in making system-level tradeoffs that optimize the fee, functionality and different attributes to satisfy program standards. This booklet offers a brand new remedy of machine procedure layout, rather for System-on-Chip (SOC), which addresses the problems pointed out above. It starts off with a world creation, from the high-level view to the bottom universal denominator (the chip itself), then strikes directly to the 3 major construction blocks of an SOC (processor, reminiscence, and interconnect). subsequent is an outline of what makes SOC specified (its customization skill and the purposes that force it). the ultimate bankruptcy offers destiny demanding situations for procedure layout and SOC possibilities.Content:
Chapter 1 creation to the platforms technique (pages 1–38):
Chapter 2 Chip fundamentals: Time, quarter, strength, Reliability, and Configurability (pages 39–73):
Chapter three Processors (pages 74–122):
Chapter four reminiscence layout: System?on?Chip and Board?Based structures (pages 123–164):
Chapter five Interconnect (pages 165–207):
Chapter 6 Customization and Configurability (pages 208–245):
Chapter 7 software experiences (pages 246–284):
Chapter eight what is subsequent: demanding situations forward (pages 285–312):
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Extra info for Computer System Design: System-on-Chip
4. The reconfigurability of FPGAs enables in-system upgrade, which helps to increase the time in market of a product; this capability is especially valuable for applications where new functions or new standards tend to emerge rapidly. 5. The FPGA can be configured to suit a portion of a task and then reconfigured for the remainder of the task (called “run-time reconfiguration”). This enables specialized functional units for certain computations to adapt to environmental changes. 6. In a number of compute-intensive applications, FPGAs can be configured as a very efficient systolic computational array.
Direct access to global memory or another processor element’s local memory is expensive, so intermediate values are propagated through the array through local interprocessor connections. This requires that the data be distributed carefully so that the routing required to propagate these values is simple and regular. It is sometimes easier to duplicate data values and computations than it is to support a complex or irregular routing of data between processor elements. Since instructions are broadcast, there is no means local to a processor element of altering the flow of the instruction stream; however, individual processor elements can conditionally disable instructions based on local status information—these processor elements are idle when this condition occurs.
We shall explore them in more detail in the next chapter. 11 CONCLUSIONS Building modern processors or targeted application systems is a complex undertaking. The great advantages offered by the technology—hundreds of millions of transistors on a die—comes at a price, not the silicon itself, but the enormous design effort that is required to implement and support the product. There are many aspects of SOC design, such as high-level descriptions, compilation technologies, and design flow, that are not mentioned in this chapter.
Computer System Design: System-on-Chip by Michael J. Flynn, Wayne Luk